Various forms of embedded test are increasingly viewed as essential to reduce test cost. Among them, scan testing has gained broad acceptance as a reliable solution. Because of the high data activity associated with scan-based test operations, however, a circuit under test can dissipate much more power than it was designed to function under. A full-toggle scan pattern, for example, may draw several times the typical functional mode power. The excess power consumed during a test may result in thermal issues, voltage noise, or power droop, which, in turn, cause a yield loss, severe decrease in chip reliability, shorter product lifetime, or device malfunction. Abnormal switching activity may also cause fully functional chips to fail during testing because of phenomena such as IR-drop, crosstalk, or di/dt problem. Thus, reductions in the operating power of ICs in a test mode have been of concern for years.
Numerous schemes for power reduction during scan testing have been proposed. Among them, there are solutions specifically for built-in self-test (BIST). For example, the test power can be reduced by preventing transitions at memory elements from propagating to combinational logic during scan shift operations. This is achieved by inserting gating logic between scan cell outputs and logic circuits they drive. During normal operations and capture, this logic remains transparent. In another scheme, on-chip clock gating circuitry is used to selectively block scan chains while employing test scheduling and planning to further decrease BIST power in the Cell processor. In still another scheme, some test patterns generated by a linear feedback shift register (LFSR) are masked as not all produced vectors detect faults.
The advent of low-transition test pattern generators has added a new dimension to power aware BIST solutions. In a device comprised of an LFSR feeding scan chains through biasing logic and T-type flip-flop, the T-type flip-flop holds the previous value until its input is asserted and thus, the same value is repeatedly scanned into scan chains until the value at the output of biasing logic (e.g., a k-input AND gate) becomes 1. Depending on k, one can significantly reduce the number of transitions occurring at the scan chain inputs. In a dual-speed LFSR consists of two LFSRs driven by normal and slow clocks, respectively, the switching activity is reduced at the circuit inputs connected to the slow-speed LFSR, while the whole scheme is still ensuring satisfactory fault coverage. Mask patterns are used in to mitigate the switching activity in LFSR-produced patterns, whereas a bit swapping achieves the same goal at the primary inputs of CUT. A gated LFSR clock may allow one to activate only half of LFSR stages at a time, thus reducing power consumption as only half of the circuit inputs change every cycle. A scheme that combines the low transition generator of (handling easy-to-detect faults) with a 3-weight PRPG (deployed to detect random pattern resistant faults) can also be used to reduce switching activity during BIST-based testing. There are also schemes suppressing transitions in LFSR-generated sequences by either statistical monitoring or injecting intermediate and highly correlated patterns. Finally, a random single-input change generator can produce low power patterns in a parallel BIST environment.